This invention pertains generally to the field of fiber optic communication systems and more particularly to the use of integrated optical components and optical subsystems in such systems. Specifically, the invention relates to photonic delay-line time-slot interchangers employing cascade-structured integrated optical switches.
Several recent articles cited above have discussed the design and performance of photonic time-slot interchangers with fiber-loop delay lines. FIG. 1 illustrates the general structure and functionality of a photonic time-slot interchanger. These articles have reported that the number of time slots which can be interchanged is limited by the internal signal-to-noise ratio (ISNR) or the signal-to-crosstalk ratio (SXR) of the time-slot interchanger systems.
One of the key components of such systems is the optical switch. The ISNR or the SXR of a photonic time-slot interchanger has a strong dependence on the loss and extinction ratio of the optical switches in the fiber loops. Using the ideal optical switch, with zero loss and zero crosstalk, the SXR approaches infinity. For the near term, the most promising optical switch for such applications is the integrated-optic electrooptic switch, such as the directional coupler switch (including uniform delta-beta, reverse delta-beta or other electrode designs), or the cross-shaped digital switch. Thompson and Giordano have implemented a time-slot interchanger system using reverse delta-beta directional coupler switches for handling three time slots. (R. A. Thompson and P. P. Giordano, "An experimental photonic time-slot interchanger using optical fibers as re-entrant delay-line memories", J. Lightwave Tech. Jan. 1987).
R. A. Thompson ("Architectures with improved signal-to-noise ratio in photonic systems with fiber loop delay lines", IEEE J. Selected Areas in Commun., August 1988) proposed several designs and showed analytically that the SXR could be improved by using architectural designs.
FIG. 2 shows a first embodiment of a photonic time-slot interchanger 20 using N reentrant fiber-loop memories 22, as described by Thompson. The 1.times.N optical switch 21 and the N.times.1 optical switch 23 are series of N interconnected 1.times.2 optical switches 28. Each fiber-loop memory includes a 2.times.2 optical switch 29 which are implemented by lithium niobate directional couplers. A clock 25 controller 26 and drivers 27 complete the system.
A second embodiment of the photonic time-slot interchanger of FIG. 2 (not shown) is substantially similar to that of FIG. 2, except that it uses N+1 reentrant fiber-loop memories 22 for an N-slot system, the extra-loop design, as described by Thompson. The second embodiment also has a 1.times.(N+1) optical switch 21 and an (N+1).times.1 optical switch 23.
A third embodiment of the photonic time-slot interchanger of FIG. 2 (not shown) is substantially similar to that of FIG. 2, except that it replaces the reentrant fiber-loop memories 22 with the general series feedforward structure of FIG. 3 to provide the minimal-transversal design, as described by Thompson.
In his three designs, i.e., the re-entrant loop, the extra loop, and the minimal-transversal designs, which are shown in FIGS. 2 and 3 respectively, Thompson uses conventional directional coupler switches. Generally speaking, these switches have quite limited extinction ratios. In controlling the photonic time-slot interchanger, automatic electronic circuits must be used. However, since individual voltage adjustments are generally needed for directional coupler switches due to the nonuniformity of the fabricated devices and the drifting of the operating point, automatic control has been difficult and unreliable.